Tape-Out Ready Physical Design & EDA Support

The contract requires the production of GDSII and OASIS layout files along with IBIS models, S-parameters, and eye diagrams to validate signal and power integrity for tape-out readiness on Intel’s 18A process node. All deliverables must meet stringent industry standards to ensure the physical design is fully optimized and compliant for manufacturing, with a focus on minimizing signal degradation, electromagnetic interference, and power delivery issues. The work must be executed with precision to support seamless transition from design to fabrication, ensuring the final product meets electrical and performance targets. This is a subcontract under NAICS code 541714, issued by the Department of Defense via FA8002 Saf Aq, with a response deadline of July 23, 2026, and a posting date of July 8, 2026. The place of performance and specific point of contact are not detailed in the provided data, but the scope clearly demands advanced EDA expertise and close alignment with Intel’s 18A process requirements. All deliverables must be submitted in recognized industry formats and accompanied by verification data to confirm compliance with reliability and performance benchmarks necessary for defense applications.