A Signal Frequency Channelizer ASIC

Far infrared and sub-mm astronomy instruments employ MKIDs for measurements of ultimate sensitivity and resolution exceeding 10,000 pixels. Detector array readout requires RF frequency division multiplexing and complex multichannel signal processing. An off-the-shelf ADC in combination with an FPGA based DSP block used for spectrum channelizing and power level measuring in each frequency bin suffers of unacceptable system size, weight and power (SWaP). We propose to develop an ASIC which will channelize signal spectrum into 2048 frequency bins. These bins can be tuned with 0.954KHz per bin resolution to any portion of the spectrum within -500MHz to +500MHz. The ASIC will include two 12-bit 1GS/s ADCs, a data alignment and demultiplexing block, 2048 DFT cells, an accumulation/readout block and a high-speed Ethernet interface. Additionally, the ASIC will include a PLL for clock synthesis, a debug memory for storing of short duration raw digitized data or debug data from the DSP block. A digital control subsystem will handle the entire ASICs operation and communication. In addition to minimized SWaP, the ASIC will tolerate TID and SEE. Within Phase I, we proved the ASIC implementation feasibility. Phase II will result in the silicon proven ASIC prototypes. Pacific Microchip Corp. will design, fabricate and test a dual-sideband tunable 2048-bin digital channelizer ASIC for MKID readout. Detector array readout requires to apply RF frequency division multiplexing and subsequent signal challenging. An approach employing an off-the-shelf ADC and an FPGA based DSP function used for frequency band channelizing and power level measuring in frequency bins suffers from large SWaP, especially in applications that require to readout a large number of detectors. The proposed ASIC will include: two 12-bit 1GS/s ADCs, a data alignment and demultiplexing block, 2048 DFT cells, and an accumulation/readout block with an Ethernet interface. The ASIC will also include a PLL for clock synthesis, and a debug memory. In addition to minimized SWaP, the proposed ASIC will be able to operate at temperature below -40C and feature immunity to TID effects and tolerance to SEEs. The strategic objective of Phase II project is to finish the design, fabricate and test the proposed ASIC which would meet NASA requirements. The specific objectives: 1) To design analog/mixed signal circuits, digital blocks and their layouts. 2) To integrate the circuits and layouts – to assemble the chip. 3) To complete the chip’s LVS, DRC reliability, latch-up, antenna and all other verifications. 4) To fabricate the die based on the 28nm HPC+ CMOS process. 5) To package chips using a previously developed chip carrier. 6) To design, fabricate and assemble the PCB and develop the GUI for automation of the chip testing. 7) To test and characterize the ASIC, identify any problems in the ASIC’s design. 8) To prepare the specifications for the ASIC part. 9) To collect and organize the data and to provide the project report. Proposed Deliverables: Interim reports Final project report Fabricated and assembled ASIC parts The ASIC testing/evaluation board
Benefits: Single photon sensitive focal planes from IR to X-ray Earth, balloon and space-based telescopes and radiometers Telescopes for FIR Probe and Flagship missions Missions: JPSS-2, 3, 4, PACE and TROPICS Spectrometer systems for remote sensing MKID based single photon sensitive imaging for remote sensing Specialized spectrometers for exploration of temperature, vapor and pollutants Infrared, visible light, UV and THz imaging in surveillance and security systems Generic spectrometers and spectrum analyzer instruments