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Edge Hardware Optimization and Validation

Open

SBIR / STTR

Response Deadline12/02/2026, 05:00:00 AM UTC

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

AI Contract Overview

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The Edge Hardware Optimization and Validation subcontract supports US Navy STTR projects by providing embedded edge hardware and CPU configurations for prime contractors. The primary objective is to test SI/ML models on low-cost hardware to measure and minimize power consumption and memory footprints, thereby reducing computational overhead to ensure deployment is field-friendly. The successful contractor will be responsible for delivering detailed performance metrics and a comprehensive hardware validation report. This opportunity is a total small business set-aside under NAICS code 541330, specifically mandated for SBIR/STTR participants with fewer than 500 employees. Due to the nature of the work for the Department of Defense, CMMC Level 2 compliance is a mandatory requirement. The solicitation was posted on November 4, 2026, with a response deadline of December 2, 2026.

General Info

US Navy subcontract for edge hardware optimization, SI/ML testing, and CMMC Level 2 compliance.

Agency

Department of Defense → United States Navy

NAICS

541330 - Engineering Services

Place of Performance

Not specified

Set-Aside

SBA

Documents

This scope was carved out of DON27TZ02-NV002.

The full solicitation package (2 documents), including the RFP, is on the prime solicitation, not on this scope.

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Field-Friendly Artificial Intelligence and Machine Learning Systems

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Timeline

PostedNov 4

subcontract

Response DeadlineDec 2

Submission deadline

Response Deadline

12/02/2026, 05:00:00 AM UTCin 26 days

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Organization & Contact Information

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AgencyDepartment of Defense → United States Navy

ContactsNo contacts available

OfficeN/A

Organization / AgencyDepartment of Defense → United States Navy

Office AddressN/A

ContactsNo contact information available

Full Description

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Supplies and integrates embedded edge hardware and CPU configurations for prime contractors on US Navy STTR projects. Tests SI/ML models on low-cost CPU and embedded hardware to measure and reduce memory footprints and power consumption. Validates field-friendly deployment by reducing computational overhead. Requires CMMC Level 2 compliance. Delivers a hardware validation report and performance metrics.

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