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RFI Mitigating (RFIM) Receiver Backend ASIC

Active
NASA-SBIR-112998SBIR / STTR

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

General Info

Agency

National Aeronautics and Space Administration → NASA SBIR/STTR ProgramView Agency

Contract Value

$850,000

NAICS

N/A

Place of Performance

Pasadena, AZ, 91109, USA

Set-Aside

SBA

Awardee

Jet Propulsion LaboratoryView Profile

Award Issued Date

Documents

(2)

S1.03-3822 RFI Mitigating (RFIM) Receiver Backend ASIC

PDFrfi

80NSSC20C0150 - Phase II-E progress report for RFIM Receiver Backend ASIC

PDFprogress-report

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Timeline

PhaseSolicitation
Posted

Solicitation

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Organization & Contact Information

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AgencyNational Aeronautics and Space Administration → NASA SBIR/STTR Program
Contacts4 people available
OfficeUSA
Organization / Agency
National Aeronautics and Space Administration → NASA SBIR/STTR Program
View Agency Profile
Office AddressUSA
Contacts
Lynn M TorresProject Manager
Phaneendra BikkinaPrincipal Investigator
Jason L KesslerProgram Director
Carlos TorrezProgram Manager

Interested Companies (2)

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Alphacore
Tempe, AZ
Jet Propulsion Laboratory
Pasadena, CA

Full Description

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According to the solicitation topic S1.03, NASA requires a low power, low mass, low volume, and low data rate RFI mitigating receiver back end that can be incorporated into existing and future radiometer designs.Alphacore proposes to design an application specific integrated circuit (ASIC) that provides significant SWAP (size, weight and power) reduction as compared to the existing board-level systems that use COTS ADCs and FPGAs with their total mass reaching kilograms.Alphacores solution will be an ASIC that will have a5GS/S (gigasamplesper second), 10-bit, 40mW, radiation hard ADC and a 256-channel back-end digital signal processing (DSP) block consuming 100mW. The ASIC will be developed in a small-geometry CMOS silicon on insulator (SOI) technology (28nm) that is inherently tolerant to relatively high total ionizing dose (at least 500krad(Si) can be expected), and has better immunity to single event effects than bulk CMOS processes (nolatchup, better upset rate due to isolation). This system greatly benefits all future NASA missions that need systems to detect interference in different bands of frequencies. The results of this work also enable applications that require low-power receivers that incorporate ADCs and back-end filters, without the need for RFI mitigation.The proposed RFIM ASIC has much higher power efficiency along with expected better radiation hardness than the currently available solutions.The embedded ADC will also be offered as a separate intellectual property (IP) design block, and thus a stand-alone ADC can be fabricated as well. The impressiverad-hardADC has, 30X lower power than the top-of-the-line space-qualified COTS ADC. Thus, the ADC itself is well-suited as an upgrade for numerous NASA missions. Radio frequency interference (RFI) is of major concern in radio astronomy and remote sensing applications, as it can reduce the sensitivity of detector by through data damage of data-loss. Therefore, NASA requires an RFI mitigation receiver backend for future remote sensing missions and instruments. The presence of RFI is especially problematic for signal detection towards, from and within the Earth. Television, frequency modulation radio transmissions, and communication signals for GPS, cellphones, and airplanes are key contributors to RFI, and thus hinders reception of faint astronomical signals,1 and limits the sensitivity of Earth-orbiting radio telescopes. 1: Evaluate test structures from Phase 1 program Alphacore has completed the design and layout of Test Chip 1 already during the Phase I period. The evaluation of Test Chip 1 will be completed in the beginning of the Phase II program. This chip contains a 5GS/s 10 bit ADC And a DSP Test block (PFB+FFT+Kurtosis Estimator) 2: Design and optimize a fieldable prototype chip 1(also called as test chip 2), that contains optimized ADC with upgraded backend DSP that has extended functionalities/features for wide range of NASA and Non-NASA applications Test Chip 2 will contain a complete, 10-bit, 5GSPS, >5GHz ADC and a polyphase filter bank with FFT followed by multiple RFIM detection and correction algorithms including Kurtosis estimator, cross frequency algorithms and spectral flattening (multiple levels). 3: Characterize Fieldable Prototype Chip (Prototype Chip 1, also called as test chip 2) that contains the complete RFI mitigating radiometer backend After completing the tapeout of Test Chip 2, Alphacore will complete testing in both Normal environment and Radiation environment. During the first quarter of Year 2 of Phase 2, Alphacore will begin the design, layout and fabrication of test board for regular testing. Meanwhile, Alphacore will complete the test board design and test setup for evaluation in radiation environment for both TID and SEE effects (as required by LEO).
Benefits: Alphacore’s solution can be incorporated into future radiometer designs used for short-term and long-term weather predictions, measuring changes in the atmosphere, ocean and land surfaces, and understanding the space environment. Future missions such as GLIMR, FARSIDE and PICO, as well as space exploration missions such as the manned missions to the Moon, followed by the Moon to Mars initiative will benefit from this solution. The technology could have been applied to Iris Version-2, Jason-3, DORIS, GMI and the NASA Space Geodesy Program. Commercial applications of the technology includes mitigation for weather satellites against interference caused by 5G communication, commercial nanosatellites for weather forecasts, maritime data and aviation data, and well as defense CubeSat constellations for missile defense and intelligence, surveillance and reconnaissance.

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