This Subcontract opportunity from Department Of Defense was posted on January 30, 2026. The submission period has ended. Browse the details below for market research, or find similar active opportunities.

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Ultra-Low-Power Logic Gate Design and Simulation

Closed

Federal

Submission Closed03/31/2026, 12:00:00 PM EDT

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

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AI Contract Overview

The Ultra-Low-Power Logic Gate Design and Simulation subcontract, issued by the Defense Advanced Research Projects Agency under the Department of Defense, focuses on the development and simulation of non-volatile logic gates such as XOR and adders. The primary technical objectives are to achieve picosecond switching speeds and attojoule-level energy consumption while demonstrating voltage gain and fanout greater than one at room temperature. This opportunity was posted on January 30, 2026, with a response deadline of March 31, 2026. Classified under NAICS code 541715, the project emphasizes high-efficiency computing components designed for extreme performance and minimal power usage.

General Info

Agency

Department Of Defense → Defense Advanced Research Projects Agcy

NAICS

541715 - Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)

Place of Performance

Set-Aside

NONE

Documents

This scope was carved out of DARPA-PA-25-07-01.

The full solicitation package (4 documents), including the RFP, is on the prime solicitation, not on this scope.

View the prime solicitation

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AI Contract Breakdown

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Timeline

PhaseClosed

PostedJan 30

subcontract

Response DeadlineMar 31

Deadline has passed

Submission Closed

03/31/2026, 12:00:00 PM EDT

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Organization & Contact Information

AgencyDepartment Of Defense → Defense Advanced Research Projects Agcy

ContactsNo contacts available

OfficeN/A

Organization / AgencyDepartment Of Defense → Defense Advanced Research Projects Agcy

Office AddressN/A

ContactsNo contact information available

Full Description

Develop and simulate non-volatile logic gates (e.g., XOR, adder) with picosecond switching speeds and attojoule-level energy consumption, demonstrating voltage gain and fanout >1 at room temperature.