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ASIC/IC Design and Verification Services

Active

Grant

Response Deadline12/02/2026, 04:00:00 PM UTC

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

AI Contract Overview

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This subcontract for ASIC/IC Design and Verification Services supports prime contractors on chip design research projects funded by the Engineering and Physical Sciences Research Council. The scope of work involves performing chip design, logic verification, and architectural simulation, with a specific focus on RTL coding, functional verification, timing analysis, and power optimization. The selected provider must utilize industry-standard EDA tools such as Cadence or Synopsys and strictly adhere to UVM methodologies to deliver verified RTL code, comprehensive verification reports, and detailed design specifications. The opportunity was posted on September 27, 2026, with a response deadline of December 2, 2026. Classified under NAICS code 541330, the contract is managed through UK Research and Innovation. Interested parties should refer to the official UKRI portal for further details regarding the doctoral focal award associated with these chip design and verification services.

General Info

Subcontract for ASIC/IC design and verification services using EDA tools and UVM methodologies.

Agency

UK Research and Innovation → Engineering and Physical Sciences Research Council (EPSRC)

NAICS

541330 - Engineering Services

Place of Performance

Not specified

Set-Aside

NONE

Documents

This scope was carved out of 205099.

The full solicitation package (2 documents), including the RFP, is on the prime solicitation, not on this scope.

View the prime solicitation

Doctoral focal award: chip design and verification

AI Contract Breakdown

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Timeline

PostedSep 27

subcontract

Response DeadlineDec 2

Submission deadline

Response Deadline

12/02/2026, 04:00:00 PM UTCin about 1 month

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Organization & Contact Information

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AgencyUK Research and Innovation → Engineering and Physical Sciences Research Council (EPSRC)

ContactsNo contacts available

OfficeN/A

Organization / AgencyUK Research and Innovation → Engineering and Physical Sciences Research Council (EPSRC)

Office AddressN/A

ContactsNo contact information available

Full Description

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Performs chip design, logic verification, and architectural simulation for prime contractors on EPSRC chip design research projects. Executes RTL coding, functional verification, timing analysis, and power optimization for ASICs or ICs using EDA tools such as Cadence or Synopsys. Adheres to UVM methodologies. Delivers verified RTL code, verification reports, and design specifications.

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