CHIPS R&D: RF Metrology for HF Transistor Models, Foundry fabrication Teledyne

The CHIPS R&D project, titled RF Metrology for HF Transistor Models and associated with Foundry fabrication Teledyne, aims to address critical deficiencies in US semiconductor manufacturing. Current challenges include poor yield, reproducibility issues, and a reliance on outdated measurement techniques and underperforming models. To resolve these gaps, the initiative proposes a comprehensive framework for developing and verifying high-frequency transistor models through new on-wafer standards, precision noise measurements for quality assurance, and enhanced characterization methods. Managed by the Department of Commerce Office of the Director, this effort focuses on creating optimal models tailored to specific technologies and implementing verification processes across frequencies using key performance indicators. The project seeks to overcome existing limitations where models are currently extracted from low-frequency measurements due to a lack of proper instrumentation and inaccurate calibration. The performance of this work is centered in Boulder, Colorado, under NAICS code 334413.