HDL Reference Design and Plugin Development

The contract requires the development of HDL reference designs and plugin files to facilitate seamless integration of custom algorithms on the VCK190 and VA601 platforms, specifically targeting AXI4-Stream and AI Engine interfaces. The work involves creating modular, reusable hardware descriptions and software plugins that enable efficient data flow and control between proprietary algorithms and the target FPGA hardware, ensuring compatibility with Xilinx’s streaming protocol and AI Engine architecture. The deliverables must support rapid deployment and validation of machine learning and signal processing functions on these platforms without requiring major redesigns of existing systems. The contract is listed as a subcontract under the Naval Research Laboratory, part of the Department of Defense, with a posting date of August 7, 2026, and a response deadline of August 11, 2026. Performance is expected to be centered in Washington, DC, with a zip code of 20036. The NAICS code 541715 indicates this is a research and development service in the computer systems design field, emphasizing the technical nature of the work. While no specific point of contact or set-aside details are provided, the focus remains on advancing defensive technology through hardware-software co-design tailored for high-throughput, low-latency signal processing applications.