This Government Contract opportunity from National Aeronautics And Space Administration was posted on July 27, 2026. The submission period has ended. Browse the details below for market research, or find similar active opportunities.
High-Speed Circuit Design & Layout Review
Contract Overview
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AI Contract Overview
The contract calls for comprehensive design validation of a 22-layer HPSC processor card, focusing on signal integrity, impedance control, and manufacturability to ensure optimal high-speed performance and production readiness. This work is critical for supporting advanced computing systems under NASA’s technical requirements, with validation tasks intended to identify and resolve potential electrical and fabrication issues before physical prototyping. The effort demands deep expertise in high-speed digital design, PCB layout analysis, and manufacturing process constraints to guarantee the card meets stringent reliability and performance benchmarks. This subcontract opportunity, issued under NAICS code 541330 for engineering services by the NASA Shared Services Center on behalf of the National Aeronautics and Space Administration, has a narrow response window closing just two days after posting on July 29, 2026. The scope requires precise technical execution with no room for ambiguity, as failure to meet validation criteria could impact mission-critical systems. While no specific location or point of contact is provided, the work likely involves close collaboration with NASA engineering teams and adherence to federal procurement standards for technical deliverables and documentation.
General Info
Agency
NAICS
Place of Performance
MSSet-Aside
Documents
This scope was carved out of 80NSSC26939777Q.
The full solicitation package (1 document), including the RFP, is on the prime solicitation, not on this scope.
PCB FABRICATION AND ASSEMBLY OF HPSC PROCESSOR CARD
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Timeline
Submission Closed
Organization & Contact Information
Full Description
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