High Temp Semiconductor Transistors for Hot DoW Environments and Electronic Warfare

The United States Air Force seeks the development of high-temperature semiconductor transistor solutions to enable electronics operation in high temperature DoW environments and improved performance in electronic warfare (EW) applications. With the continued evolution of advanced military systems operating under increasing heat loads, including those from the environment and those generated as waste-heat inside platforms, there is an increasing need for semiconductors that can function reliably at extreme temperatures. Today's commercial-off-the-shelf electronics cannot operate at temperatures more than 250°C with limited transistor count and performance, falling short of this new DoW electronics need. To bridge this technology gap, this topic solicits high temperature semiconductor electronics device and circuit solutions which can operate at temperatures at or above 500°C to address these DoW high temperature environment and electronic warfare needs. Proposed efforts must have already identified a clear DoW hot environment and/or Electronic Warfare application with a credible path to transition into the microelectronics defense industrial base. Preference will be given to solutions that have identified and target transition to an electronic warfare application while using an underlying device and circuit technology which can be adapted to a broad set of DoW high temperature electronics needs. Based on that identified application, proposed efforts should include circuit design, semiconductor device design, device fabrication, and device characterization in order to develop this technology and demonstrate its performance. Circuit design must be used to derive device performance metrics, based on 100-1,000 transistor count circuit building blocks for a future 5,000 – 100,000 transistor count integrated circuits appropriate for transition to the identified application. The desired operating temperature is at or above 500°C and operating frequency at temperature is minimum 1MHz, Target 10MHz, higher is desired. The device portion of proposed efforts should design, develop, and experimentally demonstrate transistors consistent with performance metrics determined from the circuit design effort. Solutions which can realize complementary transistor circuit topologies (meaning two types of transistors with threshold voltages of opposite polarity and carrier type) to support best-industry-practice circuit design approaches are preferred. Device failure analysis though structural, chemical, and electrical characterization methods, such as cross-sectional SEM imaging, spatially resolved energy dispersive X-ray spectroscopy, and temperature-soak in-situ electrical tests, are desired to improve transistor designs towards the circuit metrics and derived device metrics. These particular techniques are only examples, not requirements, and specific appropriate techniques should be included and justified in the proposal to support the required failure analysis. Consistent with the description above, the anticipated Technology Readiness Level (TRL) of the proposed semiconductor device and circuit solutions at the start of the project is TRL 3, denoting that analytical and experimental critical function and/or proof-of-concept has been demonstrated in past work. By the end of Phase II, the anticipated TRL is 5, component validation in a relevant environment, achieved though high temperature semiconductor device testing at or above 500°C in this context.