Process development for APSM sets of overlay wafers

This project, titled Process development for APSM sets of overlay wafers, is a forecast initiative managed by the Department of Commerce under the Office of the Director. Based in Gaithersburg, Maryland, the effort focuses on advancing integrated circuit production by improving the measurement of 3D size, shape, and placement of structures. The goal is to replace current arbitrary methods with a scientific foundation for SEM dimensional metrology and overlay measurements, addressing existing challenges related to complex 3D structures, material variety, and low signal intensities. The initiative aims to meet current and future IRDS requirements by optimizing overlay pattern design, data acquisition, and image analysis. This will be achieved through the integration of artificial intelligence, physics-based simulation, and advanced modeling. The project is categorized under NAICS code 334413 and is coordinated through the Department of Commerce's procurement channels.