ADC/DAC Configuration Software and JESD204C Integration

The contract requires the development of software to initialize registers for analog-to-digital and digital-to-analog converters and to integrate the JESD204C high-speed serial interface for RF data acquisition and transmission on FPGA platforms. The solution must ensure precise configuration of ADC and DAC components and reliable, low-latency data transfer compliant with the JESD204C standard, enabling high-performance signal processing in defense applications. The work involves close alignment with FPGA architecture, timing constraints, and protocol implementation to support mission-critical RF systems. The contract is a subcontract issued by the Naval Research Laboratory under the Department of Defense and is classified under NAICS code 541715 for research and development in the physical, engineering, and life sciences. The place of performance is identified as Washington, DC, with a zip code of 20036. The opportunity was posted on August 7, 2026, and responses are due by August 11, 2026, at 8:00 PM Eastern Time. The solicitation does not specify a set-aside classification or point of contact, and further details are accessible through the provided SAM.gov link.