EAGER: From Mitigation to Exploitation: A Cross-Layer Co-Design Framework for Robust In-Memory Computing

Conventional computers must move data from the memory units to the process units to perform computations. For data-intensive applications such as artificial intelligence (AI), this data movement often consumes much more time and energy than the computation itself. In-memory computing (IMC), an emerging computing paradigm, addresses this challenge by performing computation directly within memory, offering the potential for dramatic improvements in speed and energy efficiency. Unlike conventional hardware, however, IMC platforms exhibit intrinsic variability arising from imperfections in memory devices and circuits. Reliable operation despite hardware imperfections is critical for applications such as autonomous vehicles and robotics, where incorrect results can have serious consequences. Existing approaches largely seek to suppress or eliminate hardware variability, often leading to inefficient designs and limited robustness guarantees. This EAGER project proposes a cross-layer framework, spanning memory devices, circuits, architectures and algorithms, that moves beyond variability mitigation toward principled exploitation. The project will (i) develop analytical tools for designing robust and resource-efficient hardware for accelerating AI and other data-intensive workloads, (ii) enable cross-layer methodologies that improve energy efficiency while reducing unnecessary hardware overhead, and (iii) train students at the intersection of electrical engineering and computer science. By establishing formal principles for variability-aware computation, this project will advance trustworthy and energy-efficient computing beyond traditional digital paradigms. Achieving this vision requires bridging a fundamental disconnect between device/circuit-level variability modeling and algorithm-level robustness theory. Robust learning typically assumes precise execution, while most existing IMC reliability research assumes algorithms will tolerate hardware variability without formal guarantees. The proposed work establishes a cross-layer analytical foundation for robust IMC through three interconnected advances. (i) Noise Propagation Theory: develop formal models that relate device/circuit-level variability to algorithmic behavior, including optimization dynamics, convergence properties, and stability, yielding robustness and correctness bounds under structured hardware variability. (ii) Noise-Aware Robust Optimization: formulate learning and mapping methodologies that explicitly incorporate hardware-induced variability into optimization objectives to improve both average-case accuracy and worst-case robustness. (iii) Cross-Layer Co-Design: establish analytical criteria for determining when stochastic effects should be suppressed and when they can be exploited, leading to provable tradeoffs among robustness, precision, and hardware cost. Together, these contributions transform IMC variability from an implementation constraint into a formally characterized design dimension. If successful, the project will establish foundational principles for designing robust computing systems that effectively manage and exploit hardware variability. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.