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Heterogeneous Integration & 3D Packaging

Active

Federal

Response Deadline10/01/2029, 05:59:00 AM UTC

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

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This contract focuses on the development of advanced semiconductor packaging technologies, specifically targeting chiplet integration, through-silicon vias (TSVs), interposers, and 3D stacking. These innovations are aimed at enhancing high-performance computing and artificial intelligence applications, reflecting a strategic emphasis on improving processing capabilities and efficiency through heterogeneous integration techniques. The work is positioned as a subcontract under the NAICS code 334418, which pertains to semiconductor manufacturing. Issued by the Department of Energy, the contract encourages technological advancement in packaging to support next-generation computing architectures. The solicitation was posted in March 2026, with a response deadline set for October 1, 2029, allowing a broad timeframe for participation. The place of performance is identified by the zip code 87123, though specific location details are not provided. This contract highlights the government's commitment to fostering innovation in semiconductor packaging to meet the growing demands of AI and high-performance computing sectors.

General Info

Develop advanced semiconductor packaging technologies for chiplet integration and 3D stacking to enhance AI computing.

Agency

Department Of EnergyView Agency

NAICS

334418 - Printed Circuit Assembly (Electronic Assembly) ManufacturingView NAICS

Place of Performance

NM, 87123, USA

Set-Aside

NONE

Documents

(0)

No documents available

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Timeline

PostedMar 25

subcontract

Response DeadlineOct 1

Submission deadline

Response Deadline

10/01/2029, 05:59:00 AM UTCin about 3 years

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Organization & Contact Information

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AgencyDepartment Of Energy

ContactsNo contacts available

OfficeN/A

Organization / Agency

Department Of Energy

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Office AddressN/A

ContactsNo contact information available

Full Description

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Development of advanced packaging techniques including chiplet integration, through-silicon vias (TSVs), interposers, and 3D stacking for high-performance computing and AI applications.

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