CMOS Foundry and Integration Partner
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This subcontract opportunity with the Office of the Secretary of Defense seeks a CMOS Foundry and Integration Partner to support DoD SBIR research projects. The selected partner will be responsible for the fabrication of CMOS read-out integrated circuits and the monolithic integration of graphene sensing layers. Key technical requirements include the execution of photolithography, etching, deposition, and integration onto CMOS wafers, culminating in the delivery of FPA prototypes. The provider must maintain a Class 100 cleanroom equipped with steppers, mask aligners, and e-beam evaporation capabilities while adhering to all semiconductor industry and hazardous material standards. This is a Total Small Business Set-Aside under NAICS code 334413, requiring the partner to have fewer than 500 employees to meet SBIR/STTR mandates. Responses are due by October 7, 2026.
General Info
Agency
NAICS
Place of Performance
Not specifiedSet-Aside
Documents
This scope was carved out of OSW26BZ06-DV027.
The full solicitation package (1 document), including the RFP, is on the prime solicitation, not on this scope.
Monolithic Graphene–CMOS Broadband (UV-LWIR) Focal Plane Arrays for target detection in low-light conditions
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