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This Government Contract opportunity from Department Of Defense was posted on December 2, 2022. The submission period has ended. Browse the details below for market research, or find similar active opportunities.

Strategic & Spectrum Missions Advanced Resilient Trusted Systems (S2MARTS) Request for Solutions (RFS) in support of Microelectronics Commons (The Commons) Project No. 22-16

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N0016423SNB20Federal

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

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NAICS: 541713
SBIR / STTR
Development of Ultrafast Nonvolatile Memory Based on Sliding Ferroelectricity in Moiré Polar Homostructures
Solicitation # OSW26TZ06-NV005
Solicitation OSW26TZ06-NV005, issued by the Office of the Secretary of Defense, seeks the development of ultrafast, high-endurance, nonvolatile memory technology utilizing sliding ferroelectricity in polar moiré van der Waals homostructures. The objective is to create memory devices that outperform current technologies in speed, endurance, and scalability by leveraging engineered nanoscale polar domains. The project aims for dual-use applications, specifically targeting edge computing, neuromorphic computing, and radiation-tolerant electronics. Performance will be measured by switching speed, switching energy, endurance, retention, readout fidelity, and device-to-device reproducibility. This is a total small business set-aside under the SBIR/STTR mandate for companies with fewer than 500 employees. The contract is structured in phases, with a Phase II base period of 10 to 12 months not to exceed 1,000,000 dollars, and an optional period of 10 to 12 months for an additional 1,000,000 dollars. Awardees may also request up to 50,000 dollars in Discretionary Technical and Business Assistance. Proposals must be submitted via the Defense SBIR/STTR Innovation Portal by October 21, 2026, and will be evaluated based on technical merit, innovation, investigator qualifications, and commercialization potential. Compliance with CMMC and DFARS cybersecurity standards is required to safeguard federal contract information.
Office of the Secretary of Defense

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NAICS: 541713
SBIR / STTR
Engineered Microstructures for Enhanced IR Aperture Performance
Solicitation # OSW26BZ06-NV024
The Office of the Secretary of Defense, through the Office of the Secretary of War, is soliciting proposals under the Small Business Innovation Research program for the development of engineered microstructures to enhance infrared aperture performance. The project seeks innovative powder synthesis and consolidation methods to produce IR-transparent composite ceramics at a scale exceeding 2 by 4 by 0.5 inches, with a long-term goal of producing components in the 3 by 9 inch range or larger. To be suitable for transition, the material must achieve sub-100 nm microstructural features in all phases, porosity below 0.1 percent, and Short-Wave to Mid-Wave Infrared transparency of at least 80 percent. Additionally, the composite must maintain these properties after exposure to 1200 degrees Celsius for 10 minutes and meet a thermal expansion to thermal conductivity ratio of 1.0 micrometers per Watt or less at 1000 degrees Celsius, with a target of 0.5 micrometers per Watt. This solicitation, numbered OSW26BZ06-NV024, is set aside for Small Business Concerns and offers a Phase I base value of 300,000 dollars over a 12-month period of performance, with potential additional TABA funding up to 6,500 dollars. Proposals must be submitted via the Defense SBIR STTR Innovation Portal by October 21, 2026, and must include seven specific volumes covering technical, cost, commercialization, and disclosure data. Awardees are required to maintain active registrations in SAM and the SBA Company Registry and must comply with DFARS 252.204-7012 for safeguarding covered defense information. The government will evaluate the work based on high professional standards, utilizing X-ray diffraction and scanning electron microscopy with energy dispersive spectroscopy to verify technical specifications.
Office of the Secretary of Defense

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NAICS: 541713
SBIR / STTR
Scalable Hard-mask materials with Improved Etch resistance and Low Degradation for Extreme-aspect-Ratio fabrication (SHIELDER)
Solicitation # DPA26TZ06-DV004
The Scalable Hard-mask materials with Improved Etch resistance and Low Degradation for Extreme-aspect-Ratio fabrication (SHIELDER) project is a Small Business Technology Transfer (STTR) solicitation issued by the Defense Advanced Research Projects Agency (DARPA). The objective is to develop innovative nanofabrication hard-mask materials that overcome the physical limitations of current state-of-the-art inorganic films and sputtered metals. The goal is to enable the creation of extreme high-aspect-ratio structures, specifically targeting a 100:1 ratio, with minimal sidewall roughness and precise dimensional control. These materials are intended for use across various platforms, including semiconductor, photonic, MEMS, and quantum devices, and should be compatible with standard plasma fabrication tools such as RIE, ICP, and Bosch Deep RIE. This total small business set-aside opportunity offers a primary award value of 1,500,000 dollars over a 24-month period of performance, with an additional 12-month option valued at 450,000 dollars. Proposers may also be eligible for TABA funding of up to 6,500 dollars in Phase I and 50,000 dollars in Phase II. Proposals will be evaluated on their own individual merit based on technical merit, investigator qualifications, and commercial potential. Submissions must be made via the Defense Solutions Innovation Portal by October 21, 2026. Awardees must adhere to strict security requirements, including CMMC Level 2 self-assessment certification for those handling controlled unclassified information or ITAR-regulated work.
Defense Advanced Research Projects Agency

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NAICS: 541713
SBIR / STTR
Monolithic Graphene–CMOS Broadband (UV-LWIR) Focal Plane Arrays for target detection in low-light conditions
Solicitation # OSW26BZ06-DV027
Solicitation OSW26BZ06-DV027 is a Small Business Innovation Research (SBIR) effort issued by the Office of the Secretary of Defense to develop a wafer-scale, monolithically integrated graphene-on-CMOS image sensor. The project aims to create a compact, low-power, uncooled focal plane array capable of broadband imaging from 300 nm to 10,000 nm (UV-LWIR) to enhance naval ISR target detection in low-light conditions. The primary technical objective is to retire risks associated with graphene material quality, high-yield back-end-of-line transfer, and absorber sensitization, with a specific performance goal of increasing integrated-device carrier mobility to approximately 10,000 cm²/V·s. This Direct to Phase II award has an estimated value of 2,000,000 dollars with a base period of performance of 24 months. Proposals will be evaluated based on technical approach, qualifications of key personnel, and commercial potential, with the contract likely taking the form of a Firm-Fixed-Price or Cost-Plus-Fixed-Fee agreement. Awardees must comply with strict cybersecurity and data safeguarding requirements, including R-DFARS 252.204-7012 and CMMC Phase I self-assessment standards. Submissions must be made via the DSIP portal and include comprehensive technical, cost, and commercialization volumes.
Office of the Secretary of Defense

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NAICS: 541713
SBIR / STTR
Scalable Processing of Large Area, Oriented 2-Dimensional Polymer Films
Solicitation # OSW26TZ06-NV007
Solicitation OSW26TZ06-NV007, issued by the Office of the Secretary of Defense, seeks a scalable and cost-effective method to produce large-area, oriented 2-dimensional polymer (2DP) ensemble films, such as covalent organic frameworks. The primary objective is to overcome current processing limitations that result in insoluble powders or mechanically weak films by developing a process amenable to roll-to-roll manufacturing. The goal is to achieve high structural order and orientation of individual sheets perpendicular to the film plane while minimizing defects like pinholes and stacking errors. The project is structured in three phases: Phase I requires a continuous process producing films 1-50 microns thick at a rate of 100 feet per minute; Phase II aims to increase deposition rates by 2-5 times; and Phase III focuses on scaling to manufacturing-relevant levels with highly aligned domains. This is a Total Small Business Set-Aside under the STTR program, requiring proposing firms to be registered in SAM and the SBA Company Registry. Proposals must be submitted via the Defense SBIR/STTR Innovation Portal by October 21, 2026. Evaluation is based on technical merit, innovation, personnel qualifications, and commercialization potential, with technical soundness being the most important factor. Awardees must comply with strict cybersecurity standards, including CMMC and NIST SP 800-171/172, and provide an intellectual property agreement between the small business and its research partner. All work is expected to be performed at the unclassified level and is subject to government inspection to ensure high professional standards.
Office of the Secretary of Defense

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about 2 months ago

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in about 1 hour

General Info

NAICS

541713 - Research and Development in Nanotechnology

Place of Performance

IN

Set-Aside

NONE

Documents

0

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Timeline

PhaseClosed
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Response Deadline

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Submission Closed

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Organization & Contact Information

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AgencyDepartment Of Defense → Nswc Crane
Contacts2 people available
OfficeCRANE, IN, 47522-5001, USA
Office AddressCRANE, IN, 47522-5001, USA

Full Description

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Special Notice N0016423SNB20 Agency: Department of the Navy Office: Naval Sea Systems Command Location: NSWC Crane Division Classification Code(s): - AD92 - R&D- Defense Other: Other (Applied Research/ Exploratory Development) - AD93 - R&D- Defense Other: Other (Advanced Development) - AD94 - R&D- Defense Other: Other (Engineering Development) - AE12 - R&D- Economic Growth: Employment Growth/ Productivity (Applied Research/ Exploratory Development) - AE13 - R&D- Economic Growth: Employment Growth/ Productivity (Advanced Development) - AE14 - R&D- Economic Growth: Employment Growth/ Productivity (Engineering Development) - AJ13 - R&D- General Science/Technology: Physical Sciences (Advanced Development); General Science and Technology R&D Svcs; General Science & Technology; Experimental Development - OCC 255 - Research and Development Contracts NAICS Code(s): - 541713 - Research and Development in Nanotechnology - 611310 - Colleges, Universities, and Professional Schools Response Due Date: 28 February 2023 Strategic & Spectrum Missions Advanced Resilient Trusted Systems (S2MARTS) Request for Solutions (RFS) in support of Microelectronics Commons (The Commons) Project No. 22-16 1. PURPOSE There is a need for domestic prototyping capability, including infrastructure, to accelerate technology demonstration by enabling materials, processes, devices, and architectural designs to be developed and quickly ported and re-characterized as they are transitioned from university or other R&D laboratory facilities to small-volume prototyping and then scaled up for large-scale prototyping, fabrication and production. Due to the complexity and market value of today's integrated microelectronic (ME) systems and the lack of adequate on-shore prototyping in which intellectual property (IP) can be protected, there is an urgent need to establish a network of domestic prototyping facilities to demonstrate, at-scale, the system-level benefits of innovations in microelectronics materials, processes, devices, and architectural designs. Demonstrating at-scale commercial viability is required to close the gap between university, small business and other laboratory innovations and marketplace adoption. However, at-scale prototyping is high-risk, expensive and often not readily available at scale for other than large and established companies. As a result, small and mid-size companies and universities have a great difficulty bridging the gap between research ideas and translation of those ideas into microelectronics hardware prototypes. In particular, prototyping capabilities for six technology areas that are important to the Department of Defense (DoD) will be supported with seed projects in order to partially offset prototyping facility operating costs and to give these facilities experience in supporting outside users. These areas include secure edge/Internet of Things (IoT) computing, 5G/6G technology, artificial intelligence hardware, quantum technology, electronic warfare, and commercial leap ahead technologies. While each is important to the DoD, it is also likely that these areas may have substantial dual-use marketability. By definition, a prototype developed through an OTA may include a physical or virtual model used to evaluate the technical or manufacturing feasibility or military utility of a particular technology or process, concept, end item, or system. The Government will evaluate the solutions with the intent of awarding up to nine (9) hubs under the S2MARTS Other Transaction Agreement (OTA) in accordance with 10 U.S. Code - 4022. In accordance with 10 U.S. Code - 4022 (f), and upon a determination that the prototype project (or any subsequent iterative prototyping efforts) was successfully completed under the competitively awarded OTA(s), a follow-on production contract(s) or OTA(s) may be awarded without the use of competitive procedures. 2. BACKGROUND AND SUMMARY 2.1 S2MARTS Vendors interested in responding to this RFS must be members of the S2MARTS consortium. Interested parties may visit S2MARTS.org for membership information. This project will be managed by a Naval Surface Warfare Center, Crane Division Project Manager. 2.2 PROJECT OVERVIEW Currently, significant barriers exist in the domestic ecosystem for small and mid-size businesses, start-ups, entrepreneurs, and universities to conduct microelectronics prototyping and transition technology to large-scale commercial foundries. Major barriers include: a) Lack of access to existing 200 mm and 300-mm. fabs for lab-to-fab prototyping of Silicon-based technologies; lack of access to 150 mm fabs for compound semiconductor technologies b) High capital costs for process and metrology tooling to support manufacturing of ME technologies. c) High Intellectual Property (IP) and Electronic Design Automation (EDA) design license costs. d) Lack of domestic access to chip carriers, and packaging materials to support integration of electronics including high power electronics, photonic integrated circuits (ICs), radio frequency (RF), low loss electronics, and heterogeneous integration. e) Misalignment of nontraditional defense contractors with existing government processes. f) Lack of a professional, fulltime workforce with the talent and expertise to operate and maintain small-to-large scale prototyping facilities - to include novel materials and requiring new tools and equipment. - and to support technology transition. g) Lack of federated infrastructure investment program. Microelectronics Commons is comprised of Regional Hubs, Cores, and a Consortium Manager. A Hub is a network of regional entities with lab prototyping capabilities and sources of Microelectronics talent for onshore, lab-to-fab transition of semiconductor technologies. Hub composition may include Universities, startups, incubators, Federally Funded Research and Development Centers (FFRDCs), DoD Labs, Department of Energy (DoE) Labs, semiconductor companies, Defense Industrial Base (DIB) companies, and any entity that adds value to the network. It is anticipated that entities outside of a Region may need to be part of the Hub in order for the Regional Hub to be successful. With regards to Hub composition, the technical capabilities of the Hub is the priority. Hubs have the flexibility to bring in members from any region to be successful in their lab-to-fab efforts. The goal of the Commons is to connect regional organizations through the Hub to accelerate lab-to-fab prototyping based on proximity and to strengthen local economies through a workforce that supports those regions. Achieving that goal may require capabilities external to a Region; i.e., it is not expected that Regional Hubs can be fully self-contained. Hubs will have the flexibility to incorporate a workforce development approach into their Hub model that is tailored to the needs of their regional ecosystem. A holistic approach to developing Hubs semiconductor talent pipeline is encouraged as is the consideration of partners such as community colleges, primarily undergraduate institutions (PUIs), historically black colleges and universities (HBCUs), and minority serving institutions (MSIs). Ultimately, Hubs should develop a workforce that can support current and future efforts to accelerate lab-to-fab prototyping. Hub facilities typically include <100-millimeter (mm) and <200-mm tooling for compound semiconductor and silicon-based technologies, respectively. Hubs can also generate and mature prototype candidates for Cores to scale up for subsequent potential selection by NSTC and/or industrial microelectronics companies - fabless or integrated device manufacturers (IDMs) - for commercialization. The role of the Regional Hubs is to connect researchers and designers to prototyping capabilities targeted to regional strengths in the Hub's technical topic areas. As previously stated, it is anticipated that entities outside of a region may be required in order for the Hub to be successful. Finally, Hubs will be centers of expertise for one or more of the six DoD technology areas, as well as other tech areas they deem appropriate. Hubs that specialize in specific new approaches to types of logic/memory/analog/RF/photonics/ power technologies will also need specialized equipment, materials, processes, tools, and specialized staff expertise. Cores are fabs/foundries - manufacturing facilities where semiconductor devices are manufactured - and can be existing or new facilities, that have scalable capacity for prototyping beyond what the regional Hubs can provide for and are available for use by innovators that run the gamut from university and small business up to large industrial concerns. Cores typically have 300-mm capabilities for silicon-based technologies (other sizes are technology appropriate) and are facilities that can demonstrate prototypes with the volume and characteristics required to ensure reduced risk for manufacturing. Cores serve a dual function: First, they serve to further complement and advance the work of the regional Hubs; i.e., they are integral to the Hubs themselves. For example, they provide capabilities at =200 mm wafer fab for Silicon CMOS-compatible technologies and =100 mm wafer fab for compound semiconductors. Second, they serve to engage with commercial fabs and better align Regional Hubs to commercial processes to facilitate transition of technologies. As such, Cores are an integral part of Hubs, and proposals from stand-alone Cores will not be accepted. Please visit the S2MARTS website at https://s2marts.org/ to review the full RFS. Contracting Office Address: 300 Hwy 361 Crane, IN 47522 United States Primary Point of Contact: Luke Duwel luke.a.duwel.civ@us.navy.mil Phone: (812) 854-4818 Secondary Point of Contact: Matthew Summers matthew.s.summers@navy.mil Phone: (812) 854-8756

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