Scalable Hard-mask materials with Improved Etch resistance and Low Degradation for Extreme-aspect-Ratio fabrication (SHIELDER)

Next-generation defense-relevant microsystem technologies, such as 3D integrated circuits, high-density memory arrays, MEMS inertial sensors and RF filters, and integrated photonic devices, rely on the precise manufacturing of extreme high-aspect-ratio features within a chip [1-3]. Furthermore, emerging architectures for multiferroic memory and logic components, such as those being pioneered under DARPA's Fast and Curious program [4], stand to benefit immensely from novel process flows capable of delivering deep trenches with ultra-low line-edge roughness. As critical dimensions of these devices continue to shrink to improve performance or reduce size and cost, the ability to accurately transfer lithographic patterns into underlying substrates (such as silicon) via aggressive plasma etching has become a primary manufacturing bottleneck. Current state-of-the-art (SOTA) hard masks predominantly utilize thick chemical vapor deposition (CVD) inorganic films (e.g. silicon dioxide, silicon nitride) or sputtered metals. These conventional technologies face fundamental physical limitations at extreme scales. To achieve the necessary etch resistance, standard masks must be deposited with significant thickness, which induces high stress, structural instability, pattern distortion, and reduced feature fidelity during the etch process. Furthermore, conventional metal masks exhibit polycrystalline structures; their inherent grain boundaries erode unevenly under ion bombardment, propagating severe line-edge and sidewall roughness that degrades the electrical and structural integrity of the final device. This STTR topic seeks highly innovative masking materials that disrupt the current paradigm. The goal is to identify and develop solutions that deliver ultra-high etch selectivity while addressing the weaknesses of current SOTA solutions. Proposed approaches should inherently bypass the degradation mechanisms of traditional masks by utilizing low-dimensional, continuously ordered, inherently grain-free and/or self-regenerating structures to ensure pristine pattern transferring with low line-edge roughness even when subjected to aggressive, high-density plasma [5-7]. Solutions do not have to be limited to silicon processing and may target compound semiconductors, wide-bandgap materials, piezoelectric substrates, ceramics, heterogeneous material stacks or any other microsystems platform relevant to the Department of War (DoW). Compatibility with existing or minimally-modified reactive ion etching (RIE), inductively coupled plasma (ICP), Bosch Deep RIE (DRIE), or related plasma fabrication tools is strongly preferred. Proposers should identify the underlying physical mechanisms responsible for enhanced pattern-transfer performance and demonstrate a clear path toward scalable manufacturing. Metrics of interest include improvements in etch selectivity, maximum achievable aspect ratio, critical-dimension control, sidewall roughness, mask thickness reduction, process throughput, and compatibility with wafer-scale manufacturing.