Verilog Source Code Development for BCH Encoder/Decoder IP

The contract involves the development and delivery of synthesizable Verilog source code for a BCH encoder/decoder intellectual property block designed for integration into NASA’s Laser Communications Relay Demonstration system. The deliverable must meet stringent aerospace standards for reliability and performance, ensuring compatibility with existing spacecraft communication architectures and capable of operating in the harsh radiation environment of space. The IP block must be fully documented, testable, and ready for synthesis and implementation in field-programmable gate array or application-specific integrated circuit formats without requiring significant redesign. The opportunity is issued as a subcontract under NASA Shared Services Center, with a NAICS code of 541511 for computer systems design services. Responses are due by July 14, 2026, and the requirement is open for submissions following the posted date of July 9, 2026. The work is intended to support critical data transmission capabilities for NASA’s deep space and Earth-orbiting missions, making technical accuracy, timing, and verification rigor essential. Performance may involve coordination with NASA engineering teams to validate functionality and environmental robustness under operational constraints.