Low-D Device and Full-Chip Prototype Demonstration

This subcontract, titled Low-D Device and Full-Chip Prototype Demonstration, is issued by the National Science Foundation's Directorate For Technology, Innovation, & Partnerships. The project focuses on the design and fabrication of functional full-chip level prototypes for prime contractors on NSF ELEGANT projects. The primary objective is to achieve a 10X improvement in power, performance, area, and cost over standard CMOS nodes through device-circuit co-designs, variability-aware circuit sizing, and standard-cell characterization using advanced fabrication and testing equipment. The contract requires strict compliance with CHIPS Act restrictions and falls under NAICS code 334413. Interested parties must respond by December 18, 2026, to provide the required functional full-chip level prototypes.