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Technical Support & Integration for IEEE 1800.2 and SystemVerilog Verification

Active

Federal

Response Deadline09/03/2026, 03:00:00 PM UTC

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

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This subcontract, issued by the Department of Defense under the agency W6QK Acc-Rsa, focuses on providing technical support and integration for IEEE 1800.2 and SystemVerilog verification. The primary objective is to maintain compatibility with IEEE 1800.2 test benches and SystemVerilog assertions to ensure seamless integration with functional coverage metrics and existing FPGA/ASIC verification workflows. The opportunity was posted on August 28, 2026, with a response deadline of September 3, 2026. The work is designated for performance at Redstone Arsenal, zip code 35898, and falls under NAICS code 541715.

General Info

DoD subcontract for IEEE 1800.2 and SystemVerilog technical support at Redstone Arsenal.

Agency

Department Of Defense → W6QK Acc-RsaView Agency

NAICS

541715 - Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)View NAICS

Place of Performance

Redstone Arsenal, AL, 35898, USA

Set-Aside

NONE

Documents

This scope was carved out of PANRSA26P0000040353.

The full solicitation package (2 documents), including the RFP, is on the prime solicitation, not on this scope.

View the prime solicitation

QUESTA ONE

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Timeline

PostedAug 28

subcontract

Response DeadlineSep 3

Submission deadline

Response Deadline

09/03/2026, 03:00:00 PM UTCin 5 days

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Organization & Contact Information

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AgencyDepartment Of Defense → W6QK Acc-Rsa

ContactsNo contacts available

OfficeN/A

Organization / Agency

Department Of Defense → W6QK Acc-Rsa

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Office AddressN/A

ContactsNo contact information available

Full Description

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Provide technical support to maintain compatibility with IEEE 1800.2 test benches and SystemVerilog assertions, ensuring seamless integration with existing FPGA/ASIC verification workflows and functional coverage metrics.

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