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Foundry (TBD)

Active
Federal

Contract Overview

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The Department of Commerce is forecasting a project focused on overcoming critical performance, yield, and reproducibility challenges in advanced semiconductor transistor technology. To address the limitations of legacy measurement techniques and underperforming models currently used by US chip makers, the initiative aims to establish a robust framework for developing and verifying high-frequency transistor models. This comprehensive approach includes the implementation of new on-wafer standards and calibration, precision noise measurements for quality assurance, and the creation of technology-tailored models verified across frequencies using key performance indicators. This forecast is categorized under NAICS code 334413 and is slated for performance in Boulder. Interested parties can coordinate with the Department of Commerce, specifically through the designated point of contact, Nathali Medina, or the Office of Small and Disadvantaged Business Utilization. The project represents a strategic effort to modernize semiconductor characterization and modeling to ensure higher precision and reliability in chip manufacturing.

General Info

Commerce project to improve semiconductor transistor modeling and measurement standards in Boulder.

Agency

Department of Commerce

NAICS

334413 - Semiconductor and Related Device Manufacturing

Place of Performance

BOULDER, CO, USA

Set-Aside

NONE

Documents

0

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Timeline

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forecast

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Organization & Contact Information

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AgencyDepartment of Commerce
Contacts2 people available
OfficeN/A
Organization / Agency
Department of Commerce
Office AddressN/A
Contacts

Full Description

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Advanced semiconductor technology has led to continuous performance improvements in transistors. However, many iterations are needed to obtain optimal performance and the yield and reproducibility is incredibly poor. Furthermore, US chip makers are ill-equipped with legacy measurement techniques and underperforming models. We propose a robust path to develop and verify high-frequency transistor models: 1) new on-wafer standards and calibration, 2) precision noise measurements for transistor quality assurance, 3) improved characterizations, 4) optimal models tailored to a given technology, and 5) transistor model verification across frequency with key performance indicators.

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