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Quantum Hardware Concept & Engineering Consultant

Active
Federal

Contract Overview

Solicitation details, issuing organization, response deadlines, documents, and interested companies for this government contract opportunity.

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The Quantum Hardware Concept and Engineering Consultant subcontract supports DARPA research projects by providing theoretical design and engineering analysis for a utility-scale fault-tolerant quantum computer. The scope of work includes developing revolutionary hardware design approaches, engineering physical architectures for fault tolerance, and producing technical graphics for the Stage A system concept report. These tasks are executed using high-performance computing clusters and quantum simulation software to deliver comprehensive technical design specifications and architecture diagrams. This opportunity is managed under NAICS code 541715 for the Defense Advanced Research Projects Agency within the Department of Defense. Interested parties must meet CMMC Level 1 requirements to be eligible. The solicitation was posted on July 29, 2026, with a response deadline of November 30, 2026.

General Info

DARPA subcontract for fault-tolerant quantum computer design and engineering analysis.

Agency

Department Of Defense → Defense Advanced Research Projects Agcy

NAICS

541715 - Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)

Place of Performance

VA

Set-Aside

NONE

Documents

This scope was carved out of DARPA-PA-26-02-02.

The full solicitation package (12 documents), including the RFP, is on the prime solicitation, not on this scope.

View the prime solicitation

Quantum Benchmarking Initiative Topic (QBIT) Stage A

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Timeline

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Organization & Contact Information

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AgencyDepartment Of Defense → Defense Advanced Research Projects Agcy
ContactsNo contacts available
OfficeN/A
Organization / AgencyDepartment Of Defense → Defense Advanced Research Projects Agcy
Office AddressN/A
ContactsNo contact information available

Full Description

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Performs theoretical design and engineering analysis for a utility-scale fault-tolerant quantum computer for prime contractors on DARPA research projects. Develops revolutionary hardware design approaches, engineers physical architectures for fault tolerance, and creates technical graphics for the Stage A system concept report. Utilizes quantum simulation software and HPC clusters. Requires CMMC Level 1. Delivers technical design specifications and architecture diagrams.

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