Process development for APSM sets of overlay wafers
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The Department of Commerce is forecasting a project titled Process development for APSM sets of overlay wafers to address critical challenges in integrated circuit production. The initiative focuses on improving the measurement of 3D size, shape, and placement of structures with atomic-level precision, specifically targeting the limitations of current scanning electron microscope overlay measurements caused by complex structures and low signal intensities. The project aims to replace arbitrary measurement methods with a scientific foundation utilizing artificial intelligence, physics-based simulation, and modeling to optimize overlay patterns and image analysis. This effort is designed to meet current and future IRDS requirements and will be performed in Gaithersburg, under NAICS code 334413.
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GAITHERSBURG, MD, USASet-Aside
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